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rev. 1.0 1/14 copyright ? 2014 by silicon laboratories si80xx-1kv si80xx-1kv 1 k v t hree to s ix -c hannel d igital i solators features applications description silicon lab's family of low-power digital isolators are cmos devices offering substantial data rate, prop agation delay, power, size, reliability, and external bom advantages over legacy isolation technologies. the operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performa nce. all device versions have schmitt trigger inputs for high noise immunity and only require vdd bypass capacitors. data rates up to 10 mbps are supported, and all devices achieve propagation delays of less than 65 ns. enable inputs provide a single point control for enabling and disabling output drive. ordering options include a choice of 1kv rms isolation ratings. ? high-speed operation ?? dc to 10 mbps ? no start-up init ialization required ? wide operating supply voltage ?? 3.15 C 5.5 v ? up to 1000 v rms isolation ? high electromagnetic immunity ? low power consumption (typical) ?? 2.3 ma per channel at 10 mbps ? tri-state outputs with enable ? schmitt trigger inputs ? default high or low output ? precise timing (typical) ?? 40 ns propagation delay ?? 20 ns pulse width distortion ?? 100 ns minimum pulse width ? transient immunity 50 kv/s ? aec-q100 qualification ? wide temperature range ?? C40 to 125 c ? rohs-compliant packages ?? qsop-16 ? industrial automation systems ? medical electronics ? hybrid electric vehicles ? isolated adc, dac ? power inverters ? communication systems ordering information: see page 18.
si80xx 2 rev. 1.0
si80xx rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2. undervoltage lo ckout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4. fail-safe operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. pin descriptions (si8030/35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. pin descriptions (si8040/45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. pin descriptions (si8050) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. pin descriptions (si8055) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. pin descriptions (si8065) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10. package outline: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11. land pattern: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12.1. top marking (16-pin qsop ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 12.2. top marking expl anation (16-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
si80xx 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions parameter symbol min typ max unit ambient operating temperature* t a C40 25 125 oc supply voltage v dd1 3.15 5.5 v v dd2 3.15 5.5 v *note: the maximum ambient temperature is dependent on data fr equency, output loading, num ber of operating channels, and supply voltage. table 2. electrical characteristics (v dd1 = 3.15 to 5.5 v, v dd2 = 3.15 to 5.5 v, t a = C40 to 125 oc) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 2.65 2.80 3.05 v vdd undervoltage threshold vdduvC v dd1 , v dd2 falling 2.2 2.50 2.75 v vdd undervoltage threshold hysteresis vdd hys 270 mv positive-going input threshold vt+ all inputs rising 1.4 1.6 1.9 v negative-going input threshold vtC all inputs falling 1.0 1.2 1.4 v input hysteresis v hys 0.40v high level input voltage v ih 2.0 v low level input voltage v il 0.8v high level output voltage v oh loh = C4 ma v dd1 ,v dd2 C 0.4 4.8 v low level output voltage v ol lol = 4 ma 0.2 0.4 v input leakage current i l 10a output impedance 1 z o 50 ? enable input high current i enh v enx =v ih 2.0a enable input low current i enl v enx =v il 16a supply current (dc) v dd1 v dd2 v i =0, 1 c l =15pf 4.4 7.5 7.5 10 ma ma notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channe l resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
si80xx rev. 1.0 5 figure 1. enable timing diagram supply current (10 mbps) v dd1 v dd2 v i =5mhz c l =15pf 4.4 9.4 7.5 12 ma ma maximum data rate 0 10 mbps minimum pulse width 100 ns propagation delay t phl , t plh see figure 2 20 40 65 ns pulse width distortion |t plh C t phl | pwd see figure 2 20 30 ns propagation delay skew 2 t psk(p-p) 2030ns channel-channel skew t psk 2030ns output rise time t r c l =15pf see figure 2 2.5 4.0 ns output fall time t f c l =15pf see figure 2 2.5 4.0 ns common mode transient immunity cmti v i =v dd or 0 v v cm = 1500 v (see figure 3) 35 50 kv/s enable to data valid t en1 see figure 1 10 ns enable to data tri-state t en2 see figure 1 10 ns start-up time 3 t su 40s table 2. electrical characteristics (continued) (v dd1 = 3.15 to 5.5 v, v dd2 = 3.15 to 5.5 v, t a = C40 to 125 oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channe l resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output. enable outputs t en1 t en2
si80xx 6 rev. 1.0 figure 2. propagation delay timing figure 3. common mode transient immunity test circuit typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v oscilloscope 3.15 ? to ? 5.5 ? v isolated ? supply si80xx vdd2 output 3.15 ? to? 5.5 ? v supply high voltage surge generator vcm ? surge output high voltage differential probe gnd2 gnd1 vdd1 input input ? signal switch input output isolated ? ground
si80xx rev. 1.0 7 table 3. thermal characteristics parameter symbol qsop-16 unit ic junction-to-air thermal resistance ? ja 105 oc/w table 4. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg C65 150 oc ambient temperature under bias t a C40 125 oc junction temperature t j 150c supply voltage v dd1 , v dd2 C0.5 7.0 v input voltage v i C0.5 v dd + 0.5 v output voltage v o C0.5 v dd + 0.5 v output current drive channel i o 22ma latchup immunity 3 100v/ns lead solder temperature (10 s) 260 oc maximum isolation (input to output) (1 sec) qsop-16 1500 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temper ature from C40 to 150 c. 3. latchup immunity specification is for sl ew rate applied across gnd1 and gnd2.
si80xx 8 rev. 1.0 2. functional description 2.1. theory of operation the si80xx comprises a transmitter and a receiver sepa rated by a semiconductor-based isolation barrier. the si80xx uses a high-frequency internal oscillator on the tr ansmitter to modulate digita l input signals across the capacitive isolation barrier. on the receiver side, thes e signals are demodulated back to the corresponding digital output signals that are galvanically isolated from the input. this simple and elegant architecture provides a robust data path and requires no special considerations or in itialization at start-up. a simplified block diagram for an si80xx data channel is shown in figure 4. figure 4. simplified channel diagram the transmitter consists of an input stage that latches in data from up to si x asynchronous channels, followed by a serializer stage where the data is compressed into serial data packets that are then coupled across the capacitive isolation barrier. the receiver consists of a demodulator block that converts the modulated signal back into serial data packets that are then deserialized and latched to the output. a b input latch input selector transmitter serializer demodulator deserializer receiver si80xx high frequency oscillator modulator/ packet encoder output latch packet decoder clock recovery and demodulator isolation
si80xx rev. 1.0 9 3. device operation device behavior during start-up, normal operation, an d shutdown is shown in figu re 5, where uvlo+ and uvlo- are the positive-going and negative-going thresholds re spectively. refer to table 5 to determine outputs when power supply (vdd) is not present. additionally, refer to table 6 for logic conditions when enable pins are used. table 5. si80xx logic operation v i input 1,2 en input 1,2,3,4 vddi state 1,5,6 vddo state 1,5,6 v o output 1,2 comments h h or nc p p h enabled, normal operation. lh or nc p p l x 7 l p p hi-z 8 disabled. x 7 h or nc up p l 9 h 9 upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i after start- up time, t su x 7 l up p hi-z 8 disabled. x 7 x 7 p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i after start- up time, t su , if en is in either the h or nc state. upon transition of vddo from unpowered to pow- ered, v o returns to hi-z after start-up time, t su , if en is l. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. en is the enable control input located on the same output side. 2. x = not applicable; h = logic high; l = logic low; hi-z = high impedance. 3. it is recommended that the enable inputs be connected to an external logic high or low level when the si80xx is operating in noisy environments. 4. no connects are not internally connected and can be left floating, tied to vdd, or tied to gnd. 5. powered state (p) is defined as 3.15 v < vdd < 5.5 v. 6. unpowered state (up) is defined as vdd = 0 v. 7. note that an i/o can power the die for a given side through an internal diode if its source has adequate current. 8. when using the enable pin (en) function, t he output pin state is driven into a hi gh-impedance state when the en pin is disabled (en = 0). 9. see "9. ordering guide" on page 18 for details. this is the selectable fail-safe operating mode (ordering option). some devices have default output state = h, and some have default output state = l, depending on the ordering part number (opn). for default high devices, the data channels have pull-ups on inputs/outputs. for default low devices, the data channels have pull-downs on inputs/outputs.
si80xx 10 rev. 1.0 table 6. enable input truth 1 p/n en2 1,2 operation si8030 si8040 si8050 h outputs b1, b2, b3, b4, b5, b6 ar e enabled and follow input state. l outputs b1, b2, b3, b4, b5, b6 are disabled and logic low or in high impedance state. 3 si8035 si8045 si8055 si8065 outputs b1, b2, b3, b4, b5, b6 ar e enabled and follow input state. notes: 1. enable, en, can be used for multiplexing, fo r clock sync, or other outpu t control. en is internally pulled-up to local vdd by a 16 a current source allowing it to be connected to an exter nal logic level (high or low) or left floating. to minimize noise coupling, do not connect circuit traces to en if it is left floating. if en is unused, it is recommended that it be connected to an external logic level, especially if the si80xx is operating in a noisy environment. 2. x = not applicable; h = logic high; l = logic low. 3. when using the enable pin (en) function, t he output pin state is driven into a hi gh-impedance state when the en pin is disabled (en = 0).
si80xx rev. 1.0 11 3.1. device startup outputs are held low during powerup until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs. 3.2. undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. both side a and side b each have their own undervoltage lockout monitors. each side can enter or exit uvlo independently. for example, side a unconditionally enters uvlo when v dd1 falls below v dd1(uvloC) and exits uvlo when v dd1 rises above v dd1(uvlo+) . side b operates the same as side a with respect to its v dd2 supply. see figure 5 for more details. figure 5. device behavior during normal operation input v dd1 uvlo- v dd2 uvlo+ uvlo- uvlo+ output tstart tstart tstart tphl tplh tsd
si80xx 12 rev. 1.0 3.3. layout recommendations to ensure safety in the end us er application, high voltage circ uits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, su ch as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). re fer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1. supply bypass the si80xx family requires a 0.1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, the user may also include resistors (50C300 ? ) in series with the inputs and outputs if the system is excessively noisy. 3.3.2. output pin termination the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces. 3.4. fail-saf e operating mode si80xx devices feature a selectable (by ordering option ) mode whereby the default ou tput state (when the input supply is not powered) can either be a logic high or logic low when the output supply is powered. see table 5 on page 9 and "9. ordering guide" on page 18 for more information.
si80xx rev. 1.0 13 4. pin descriptions (si8030/35) name pin# type description v dd1 1 supply side 1 power supply. gnd1 2 ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital input side 1 digital input. nc* 6 na no connect. nc* 7 na no connect. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. en2/nc* 10 digital input side 2 active high enable on si8030. nc on si8035. nc* 11 na no connect. b3 12 digital output side 2 digital output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15 ground side 2 ground. v dd2 16 supply side 2 power supply. *note: no connect. these pins are not internally connected. they can be left floating, tied to v dd or tied to gnd. v dd1 gnd1 a1 a3 nc nc gnd1 a2 v dd2 gnd2 b2 b1 nc b3 gnd2 en2/nc i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8030/35
si80xx 14 rev. 1.0 5. pin descriptions (si8040/45) name pin# type description v dd1 1 supply side 1 power supply. gnd1 2 ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital input side 1 digital input. a4 6 digital input side 1 digital input. nc* 7 na no connect. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. en2/nc* 10 digital input side 2 active high enable on si8040. nc on si8045. b4 11 digital output side 2 digital output. b3 12 digital output side 2 digital output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15 ground side 2 ground. v dd2 16 supply side 2 power supply. *note: no connect. these pins are not internally connected. they can be left floating, tied to v dd or tied to gnd. v dd1 gnd1 a1 a3 a4 nc gnd1 a2 v dd2 gnd2 b2 b1 b4 b3 gnd2 en2/nc i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8040/45
si80xx rev. 1.0 15 6. pin descriptions (si8050) name pin# type description v dd1 1 supply side 1 power supply. a1 2 digital input side 1 digital input. a2 3 digital input side 1 digital input. a3 4 digital input side 1 digital input. a4 5 digital input side 1 digital input. a5 6 digital input side 1 digital input. nc* 7 na no connect. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. en2 10 digital input side 2 active high enable on si8050. b5 11 digital output side 2 digital output. b4 12 digital output side 2 digital output. b3 13 digital output side 2 digital output. b2 14 digital output side 2 digital output. b1 15 digital output side 2 digital output. v dd2 16 supply side 2 power supply. *note: no connect. these pins are not internally connected. they can be left floating, tied to v dd or tied to gnd. v dd1 a1 a3 a4 nc gnd1 a2 v dd2 b2 b1 b4 b3 gnd2 en2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8050 a5 rf xmitr rf rcvr b5
si80xx 16 rev. 1.0 7. pin descriptions (si8055) name pin# type description v dd1 1 supply side 1 power supply. gnd1 2 ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital input side 1 digital input. a4 6 digital input side 1 digital input. a5 7 digital input side 1 digital input. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. b5 10 digital output side 2 digital output. b4 11 digital output side 2 digital output. b3 12 digital output side 2 digital output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15 ground side 2 ground. v dd2 16 supply side 2 power supply. v dd1 a1 a3 a4 gnd1 a2 v dd2 b2 b1 b4 b3 gnd2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8055 a5 rf xmitr rf rcvr b5 gnd1 gnd2
si80xx rev. 1.0 17 8. pin descriptions (si8065) name pin# type description v dd1 1 supply side 1 power supply. a1 2 digital input side 1 digital input. a2 3 digital input side 1 digital input. a3 4 digital input side 1 digital input. a4 5 digital input side 1 digital input. a5 6 digital input side 1 digital input. a6 7 digital input side 1 digital input. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. b6 10 digital output side 2 digital output. b5 11 digital output side 2 digital output. b4 12 digital output side 2 digital output. b3 13 digital output side 2 digital output. b2 14 digital output side 2 digital output. b1 15 digital output side 2 digital output. v dd2 16 supply side 2 power supply. v dd1 a1 a3 a4 a6 gnd1 a2 v dd2 b2 b1 b4 b3 gnd2 b6 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8065 a5 rf xmitr rf rcvr b5 rf xmitr rf rcvr rf xmitr rf rcvr
si80xx 18 rev. 1.0 9. ordering guide table 7. ordering guide for valid opns 1,2,3 ordering part number (opn) number of inputs/outputs default output state output enable yes/no isolation rating (kvrms) package si803x si8030aa-b-iu 3 low yes 1 qsop-16 si8030ca-b-iu 3 high yes 1 qsop-16 si8035aa-b-iu 3 low no 1 qsop-16 si8035ca-b-iu 3 high no 1 qsop-16 si804x si8040aa-b-iu 4 low yes 1 qsop-16 si8040ca-b-iu 4 high yes 1 qsop-16 si8045aa-b-iu 4 low no 1 qsop-16 si8045ca-b-iu 4 high no 1 qsop-16 si805x SI8050AA-B-IU 5 low yes 1 qsop-16 si8050ca-b-iu 5 high yes 1 qsop-16 si8055aa-b-iu 5 low no 1 qsop-16 si8055ca-b-iu 5 high no 1 qsop-16 si806x si8065aa-b-iu 6 low no 1 qsop-16 si8065ca-b-iu 6 high no 1 qsop-16 notes: 1. all packages are rohs-compliant with pea k reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. moisture sensitivity level is msl3 for qsop-16 packages. 2. all devices >1 kv rms are aec-q100 qualified. 3. si and si are used interchangeably.
si80xx rev. 1.0 19 10. package out line: 16-pin qsop figure 6 illustrates the package details for the si80xx in a 16-pin qsop package. table 8 lists the values for the dimensions shown in the illustration. figure 6. 16-pin qsop package ?
si80xx 20 rev. 1.0 table 8. package diagram dimensions dimension min max a 1.75 a1 0.10 0.25 a2 1.25 b 0.20 0.30 c 0.17 0.25 d 4.89 bsc e 6.00 bsc e1 3.90 bsc e 0.635 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-137, variation ab. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si80xx rev. 1.0 21 11. land pattern: 16-pin qsop figure 7 illustrates the recommended land pattern details for the si80xx in a 16-pin qsop package. table 9 lists the values for the dimensions shown in the illustration. figure 7. 16-pin qsop pcb land pattern table 9. 16-pin qsop land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 0.635 x1 pad width 0.40 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern sop63p602x173-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. ?
si80xx 22 rev. 1.0 12. top markings 12.1. top marking (16-pin qsop) 12.2. top marking expl anation (16-pin qsop) line 1 marking: base part number ordering options (see ordering guide for more information). 80 = isolator product series xy = channel configuration x = # of data channels (6, 5, 4, 3) y = # of reverse channels (0)* s = operating mode: a = default output = low c = default output = high v = insulation rating a=1kv line 2 marking: rttttt = mfg code manufacturing code from assembly house r indicates revision line 3 marking: yy = year ww = work week assigned by the assembly hous e. corresponds to the year and work week of the mold date. *note: si8035/45/55/65 have 0 reverse channels. 80xysv rttttt yyww
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